1. Field of the Invention
The present invention generally relates to arbitrating access to a processor bus and a peripheral bus and more particularly to a processor-based system configured for a non-concurrent mode in which a bus master is forced to acquire ownership of both the processor bus and the peripheral bus.
2. Description of the Related Art
In processor-based systems providing a processor bus and a peripheral bus such as a peripheral component interconnect (PCI) bus, transactions on the processor bus have occurred simultaneously with transactions on the peripheral bus. Similarly, processor-based systems which provide multiple peripheral buses have supported simultaneous transactions on peripheral buses. By supporting simultaneous transactions on multiple buses, conventional processor-based systems have provided optimal utilization of multiple buses.
Concurrent bus activity by multiple bus masters on multiple buses, however, has frustrated efforts to effectively debug processor-based systems. A bus transaction on one bus by a bus master frequently has unacceptable or unforeseeable affects on a simultaneous bus transaction on a different bus by another bus master. Debugging of processor-based systems with concurrent bus activity by multiple bus masters on multiple buses thus has historically been limited in favor of optimal utilization of multiple buses.